Basler A600f Instrukcja Użytkownika Pobierz pdf (Strona 25)

Basic Operation & Standard Features

BASLER A600

f 3-1

DRAFT

3 Basic Operation and

Standard Features

3.1 Functional Description

3.1.1 Overview

A600f area scan cameras employ a CMOS-sensor chip which provides features such as a full

frame shutter and electronic exposure time control.

Normally, exposure time and charge readout are controlled by values transmitted to the camera’s

control registers via the IEEE 1394 interface. Control registers are available to set exposure time

and frame rate. There are also control registers available to set the camera for single frame

capture or continuous frame capture.

Exposure start can also be controlled via an externally generated trigger (ExTrig) signal. The

ExTrig signal facilitates periodic or non-periodic start of exposure. When exposure start is

controlled by a rising ExTrig signal and the camera is set for the programmable exposure mode,

exposure begins when the trigger signal goes high and continues for a pre-programmed period of

time. Accumulated charges are read out when the programmed exposure time ends.

At readout, accumulated charges are transported from each of the sensor’s light-sensitive

elements (pixels) to a pixel memory (see Figure 3-1). As the charges are moved out of the pixels

and into the pixel memories, they are converted to voltages. There is a separate memory for each

pixel. Because the sensor has memories that are separate from the pixels, exposure of the next

image can begin while the sensor is reading out data from the previously captured image.

The pixel memories can be connected to a bus and there is one bus per vertical column. For

readout, the pixel memories are addressed row-wise by closing a switch that connects each pixel

memory in the addressed row to the column buses. As the voltages leave the column buses, they

are amplified, an offset is applied, and they are digitized by the ADCs. A variable gain control and

a 10 bit, analog-to-digital converter (ADC) are attached to the end of each column bus.

From the column buses, the digitized signals enter a horizontal output register. The 10 bit digital

video data is then clocked out of the output register, through an FPGA, and into an image buffer.

The data leaves the image buffer and passes back through the FPGA to a 1394 link layer

controller where it is assembled into data packets that comply with the “1394 - based Digital

Camera Specification” (DCAM) issued by the 1394 Trade Association. The packets are passed to

a 1394 physical layer controller which transmits them isochronously to a 1394 interface board in

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Basler A600f Instrukcja Użytkownika Strona 25